1. Field of the Invention
The present invention pertains to the field of semiconductor processing. More particularly, this invention relates to the formation of the transistor gate.
2. Background of the Related Art
Metal oxide semiconductor (MOS) technology is used to form a number of different types of devices including memory devices and microprocessors. The basic device structure forming the field effect transistor (FET) comprises an insulated gate electrically overlaying a channel region between a source and drain. The gate is an electrically conductive material separated a small distance from the underlying silicon substrate via a thin insulating layer usually made of silicon oxide. The source and drain are formed in the silicon substrate by introducing dopants in controlled amounts to make the source and drain n-type or p-type relative to the surrounding silicon. The dopants for the source and drain are inserted into the silicon using diffusion or ion implantation, both processes which require subjecting the substrate to high temperatures.
Early transistor structures were formed by first diffusing dopants into the source and drain regions and afterward forming the gate. The formation of the gate was done by depositing gate material and subsequently doing conventional photolithography patterning. Because of the need to ensure that the gate overlay the entire channel region and limitations in manufacturing tolerances, high volume manufacturing required a significant gate overlap into the source and drain to ensure that the gate adequately covered the entire channel region. For smaller device sizes the gate overlap led to significant parasitic capacitance between the gate and source region and the gate and drain region. A self-aligning manufacturing process was then developed whereby the gate itself would serve as a mask for forming the source and drain. The gate had to be formed first, so that the source and drain could be formed in alignment with the gate. A consequence of the self-aligned process was that the gate material had to be changed from metal to silicon because of the requirement that the gate withstand the high temperature processing for forming the source and drain.
In an effort to achieve smaller than 100 nm gate lengths, a process was developed whereby conventional photolithography is used to define edges onto which the dimensions of the future gate is established. This process is referred to as "litho-less". An example of this process is shown in FIG. 1. FIG. 1 a shows a silicon substrate 130. A layer of gate dielectric 120, comprising silicon oxide, is formed on the substrate 130. A layer of polycrystalline silicon (polysilicon) 110 is formed on the gate dielectric 120. In FIG. 1b, sacrificial oxide 140, comprising silicon oxide, is formed on the polysilicon. The sacrificial oxide is patterned using conventional photolithography. A layer of silicon nitride 150 is formed, as shown in FIG. 1c. FIG. 1d discloses that the silicon nitride 150 is etched to create spacers 153 and 155. The sacrificial oxide 140 and spacer 155 are removed, leaving spacer 153, as depicted in FIG. 1e. FIG. 1f shows that the exposed portion of the polysilicon 110 is removed, forming the future transistor gate 111. FIG. 1g indicates that the nitride spacer 153 is removed, exposing the remaining polysilicon, thus forming the transistor gate 111. The remainder of the transistor structure is formed using standard CMOS process.
The above litho-less process yields a minimum size transistor gate. The gate length is determined by the width of the nitride spacer 153, and the location of the gate is determined by the placement of the sacrificial oxide 140. The litho-less process gives only one effective gate length determined by the spacer thickness. The next gate length up from the minimum size is for gates defined by photolithography. The gap between the gate formed by the litho-less process and the smallest gate formed by lithography is called the "forbidden gap". The length of the litho-less gate is far smaller than that formed by lithography. This leaves a large range of transistor gate lengths within the forbidden gap that cannot be fabricated. The circuit designer is thus restricted to using the minimum size litho-less gate length or using the much larger gate lengths available using lithography. Therefore, a method for fabricating a minimum size gate and a next-to-minimum size gate using a litho-less process is desirable.